The present invention relates generally to the field of electronics and, more particularly, to skew control circuits and semiconductor devices.
A logic device may comprise several sub-circuits each having an associated clock domain. The clock domains of two sub-circuits exchanging data may be required to be in synchronization to avoid data loss and/or data faults. The sub-circuits may communicate in a hierarchical structure, wherein each sub-circuit communicates with one or more daughter sub-circuits and one mother sub-circuit (except for the root sub-circuit).
For example, a microprocessor may comprise four processor cores, whereby two of the four processor cores may exchange data via a first second level cache and the other two of the four processor cores may exchange data via a second second level cache. To allow for a data exchange between the two branches, a third level cache is provided, which communicates with the first second level cache and the second second level cache. Thus, the first second level cache has two daughter sub-circuits, namely, two of the four processor cores, and one mother sub-circuit, namely, the third level cache. The seven sub-circuits (one third level cache, two second level caches, and four processor cores) each have an associated clock domain. The clock domains are (directly or indirectly) driven by a common global clock source. However, the local clock signal of one clock domain of one sub-circuit may be early with respect to another clock-domain of a sub-circuit communicating with the aforementioned sub-circuit. The difference may also be called “skew”. Delay lines may be provided between the global clock source and the local clock sources of said clock domains to ensure proper data exchange between the sub-circuits. Additionally, other timing restrictions may have to be observed to allow for parallel skew adjusting and data transmissions.